The present invention relates to a level shifter circuit for shifting voltage of an input signal from a high voltage to a low voltage.
There is a trend in reducing power consumption in electronic circuits. For example, power consumption may be reduced by lowering the voltage of a high level signal. More specifically, a high level signal voltage that was five volts may now be a lower voltage (e.g., three volts). However, in an electronic circuitry used to drive a device, it is difficult for all circuits to be low voltage circuits. Thus, in an electronic circuitry, circuits using high voltage power supplies may be mixed together with circuits using low voltage power supplies. In such a circuit, when providing a signal for a high voltage circuit to a low voltage circuit, a level shifter circuit is used to shift the voltage of the signal (refer to Japanese Laid-Open Patent Publication No. 10-135818, FIG. 6 and Japanese Laid-Open Patent Publication No. 2003-101403, FIG. 2).
The prior art level shifter circuit described in Japanese Laid-Open Patent Publication No. 10-135818 and Japanese Laid-Open Patent Publication No. 2003-101403 will now be described with reference to FIGS. 3 and 4. FIG. 3 shows a level shifter circuit 100. Input voltage VIN is applied to an input terminal, which is connected to the drain terminal of an n-channel MOS transistor 101. Low power supply voltage VDD2 is applied to the gate terminal of the MOS transistor 101.
Three MOS transistors 105, 106, and 107 are connected in series between a supply line for the low power supply voltage VDD2 and a supply line for high power supply voltage VSS. The MOS transistors 105 and 107 are n-channel MOS transistors and the MOS transistor 106 is a p-channel MOS transistor. The drain and gate terminals of the MOS transistor 105 are connected to the supply line for the low power supply voltage VDD2. Thus, the MOS transistor 105 is normally ON and the voltage at the source terminal of the MOS transistor 105 is equal to a low drive voltage VDD, which is obtained by subtracting a threshold voltage of the MOS transistor 105 from the low power supply voltage VDD2.
The source terminal of the MOS transistor 101 that functions as a connection node A0 is connected to the gate terminals of the MOS transistors 106 and 107. Further, a connection node of the MOS transistors 106 and 107 function as an output terminal of the level shifter circuit 100. Thus, the MOS transistors 106 and 107 are switched in accordance with the voltage applied to the connection node A0 of the MOS transistor 101. Further, the power supply voltage VSS or the low drive voltage VDD is output from the output terminal of the level shifter circuit 100.
As shown in FIG. 3, the input terminal of the level shifter circuit 100 is connected to an inverter 110. The inverter 110 is connected to a supply line for a high drive voltage HVDD or a supply line for the power supply voltage VSS and uses one of these voltages as an output voltage. The gate terminal of the MOS transistor 101 is connected to the supply line for the low power supply voltage VDD2. Thus, even if the input voltage VIN increases, the voltage at the source terminal of the MOS transistor 101 does not become greater than or equal to the voltage obtained by adding a threshold voltage to the low power supply voltage VDD2. As a result, a large voltage is not applied to the gate terminals of the MOS transistors 106 and 107, and transistors of a low breakdown voltage may be used.
Output voltage VOUT of such a circuit varies in accordance with the input voltage VIN. For example, in accordance with changes in the input voltage VIN as shown in FIG. 4A, the voltage at the connection A0 is as shown in FIG. 4B. Further, the output voltage VOUT of the level shifter circuit 100 varies at intermediate values between the power supply voltage VSS and the low drive voltage VDD as shown in FIG. 4C. The intermediate values are lower than intermediate values between the power supply voltage VSS and the high drive voltage HVDD. Thus, when the input has a low level, the immunity to noise is low and the output voltage may become unstable.
A Schmitt trigger circuit is a circuit that is immune to noise (refer to, for example, Japanese Laid-Open Patent Publication No. 2004-096319, FIG. 5). The Schmitt trigger circuit described in Japanese Laid-Open Patent Publication No. 2004-096319 will now be described with reference to FIG. 5. A Schmitt trigger circuit 200 includes p-channel MOS transistors P1, P2, P3, and P4 and n-channel MOS transistors N1, N2, N3, and N4. The MOS transistors P1, P3, N3, and N1 are connected in series between a supply line for a low drive voltage VDD and a line for ground voltage GND. Input voltage VIN is applied to the gate terminal of each of the MOS transistors P1, P3, N3, and N1.
The source terminal of the MOS transistor P2 is connected to the supply line for the low drive voltage VDD, and the source terminal of the MOS transistor N2 is connected to the line for the ground voltage GND. The drain terminals of the MOS transistors P2 and N2 are connected to each other. Voltage at a connection node TY of the MOS transistors P2 and N2 becomes the output voltage VOUT. The gate terminals of the MOS transistors P2 and N2 are connected to each other at a connection node TX.
The MOS transistor P4 includes a source terminal connected to a connection node of the MOS transistors P1 and P3 and a drain terminal connected to a line for the ground voltage GND. The MOS transistor N4 includes a source terminal connected to a connection node of the MOS transistors N1 and N3 and a drain terminal connected to a supply line for the low drive voltage VDD. The gate terminals of the MOS transistors P4 and N4 are connected to the connection node TX.
When a high level signal is input to the Schmitt trigger circuit as the input voltage VIN, voltage Va at the connection node TX is shifted to a low level, and the output voltage VOUT is shifted to a high level. In this state, the MOS transistors P1, P3, N2, and N4 are inactivated, and the MOS transistors N1, N3, P2, and P4 are activated.
When the input signal shifts from a high level to a low level and the input voltage VIN exceeds a pinch-off voltage, current starts to flow through the MOS transistor P1. In this state, the drain voltage of the MOS transistor P1 is decreased due to the ON resistance balance of the MOS transistors P1 and P4. Thus, the MOS transistor P3 does not function unless the voltage further decreases. That is, the MOS transistor P3 functions when the input signal further decreases. This shifts the voltage Va to the low drive voltage VDD. Accordingly, the MOS transistor P2 is inactivated, the MOS transistor N2 is activated, and the output voltage VOUT is output at a low level. Thus, when the current supplied by the MOS transistors P1, P3, and P4 and the current supplied by the MOS transistors N1 and N3 are inverted, the output signal shifts from a high level to a low level.
When the input signal shifts from a low level to a high level, due to the MOS transistor N2, the MOS transistor N3 does not function unless the input voltage VIN becomes further higher. Thus, unlike when there is no MOS transistor N4, the voltage Va at the connection node does not change unless the input voltage VIN is higher. As a result, in the Schmitt trigger circuit 200 shown in FIG. 5, a hysteresis appears as shown in FIG. 6 and realizes the Schmitt trigger function.
The level shifter circuit 100 shown in FIG. 3 does not have a hysteresis and thus does not function as a Schmitt trigger. To shift a high level signal from a high voltage to a low voltage while being immune to noise, the Schmitt trigger circuit 200 shown in FIG. 5 may be included in the level shifter circuit 100 of FIG. 3. A level shifter circuit 300 formed in such a manner is shown in FIG. 7. In the level shifter circuit 300 of FIG. 7, the same reference numerals are given to those components that are the same as the corresponding components of the level shifter circuit 100 shown in FIG. 3 and the Schmitt trigger circuit 200 shown in FIG. 2. Such components will not be described in detail. In the level shifter circuit 300, input voltage VIN is applied to the drain terminal of the n-channel MOS transistor 101, and the input terminal of the Schmitt trigger circuit 200 is connected to the drain terminal of the n-channel MOS transistor 101. Further, the low drive voltage VDD is applied to the source terminal of the MOS transistor 105, and the voltage at the connection node TY of the Schmitt trigger circuit 200 becomes the output voltage VOUT.
The VIN-VOUT curve of the level shifter circuit 300 is shown in FIG. 8. The level shifter circuit 300 includes the Schmitt trigger function, which has hysteresis. However, even if the input voltage VIN is applied from the power supply voltage VSS (here, the ground voltage GND) to the high drive voltage HVDD, the output voltage VOUT of the level shifter circuit 300 shifts between zero volts and the low drive voltage VDD. Thus, the output voltage VOUT still changes at a voltage that is lower than the intermediate values that the input voltage VIN can take.